1. Technical Field
The present invention relates to lithography, and particularly to an exposure process.
2. Description of Related Art
Integrated circuit fabrication requires high precision techniques to achieve. Any minute errors in the fabrication process cause the fabricated wafer to be unreliable or even unusable, which worsens wafer yield.
Photolithography technology is the most important process in semiconductor fabrication. This technology prints mask patterns onto wafers for fabrication of various circuit components including MOS (metal-oxide semiconductor) components, doped areas, and other else in the integrated circuit. IC fabrication typically requires several photolithography processes to complete. Each of the photolithography processes comprises three basic steps: coating, exposure, and development.
Current photolithography technique uses fixed illumination condition, exposure energy and defocus, to print mask patterns onto wafers. However, as IC dimension shrinks, photolithography is pushed to its resolution limit due to narrow pitch of patterns. Double-exposure operation using two masks is proposed to solve the narrow pitch issue. However, this operation suffers low throughput caused by mask exchanging. Moreover, it is difficult to align the second mask precisely to the previously exposed areas on the wafers using the first mask. Furthermore, the two masks inherently possess mask errors between them, thereby worsening this double-exposure operation.